The present invention relates generally to bus structures and their operation in electronic systems to communicate between components of such systems, and, more specifically, to the use of a ring bus to do so, particularly in flash memory systems.
There are many commercially successful re-programmable non-volatile memory products being used today, particularly in the form of small form factor cards, which employ an array of flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cells formed on one or more integrated circuit chips. A memory controller, usually but not necessarily on a separate integrated circuit chip, interfaces with a host to which the card is removably connected and controls operation of the memory array within the card. Such a controller typically includes a microprocessor, some non-volatile read-only-memory (ROM), a volatile random-access-memory (RAM) and one or more special circuits such as one that calculates an error-correction-code (ECC) from data as they pass through the controller during programming and reading.
Some of the commercially available cards that utilize flash memory are the CompactFlash™ (CF) card, MultiMedia card (MMC), Secure Digital (SD) card, miniSD card, SmartMedia card, xD-Picture card, TransFlash card and Memory Stick card. Hosts include personal computers, notebook computers, personal digital assistants (PDAs), various data communication devices, digital cameras, cellular telephones, portable audio players, automobile sound systems, and similar types of equipment. Many hosts have one or more slots to receive one or more of the commercial memory card types, and/or can connect to a card reader through a Universal Serial Bus (USB) receptacle or the like. USB flash drives are also available that plug directly into a USB receptacle of a host to connect the host to the memory within the drives. Besides the memory card and flash drive implementations, flash memory systems can alternatively be embedded into various types of host systems. These and additional flash memory products are available from SanDisk Corporation, assignee of the present patent application.
Two general memory cell array architectures have primarily been implemented commercially, NOR and NAND. In a typical NOR array, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,313,421, 5,315,541, 5,343,063, 5,661,053 and 6,222,762.
The NAND array utilizes series strings of more than two memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within a large number of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on hard so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell. Examples of NAND architectural arrays and their operation as part of a memory system are found in U.S. Pat. Nos. 5,570,315, 5,774,397, 6,046,935, 6,522,580 and U.S. patent application publication No. 2003/014278.
The charge storage elements of current flash EEPROM arrays, as discussed in the foregoing referenced patents, are most commonly electrically conductive floating gates. An alternate type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of the conductive floating gate to store charge in a non-volatile manner. Several specific cell structures and arrays employing dielectric storage elements are described by Harari et al. in U.S. patent application publication No. 2003/0109093.
As in most all integrated circuit applications, the pressure to shrink the silicon substrate area required to implement some integrated circuit function also exists with flash memory cell arrays. It is continually desired to increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types of packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell and/or per storage unit or element. This is accomplished by dividing a window of a storage element charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores three bits of data per storage element, and so on. Multiple state flash EEPROM structures using floating gates and their operation are described in U.S. Pat. Nos. 5,043,940 and 5,172,338, and for structures using dielectric floating gates in aforementioned U.S. patent application publication No. 2003/0109093. Selected portions of a multi-state memory cell array may also be operated in two states (binary) for various reasons, in a manner described in U.S. Pat. Nos. 5,930,167 and 6,456,528.
Flash memory cells are erased prior to re-programming. Memory cells of a typical flash memory cell array are divided into discrete blocks of cells that are erased together. That is, the block is the erase unit, a minimum number of cells that are simultaneously erasable. Each block typically stores one or more pages of data, the page being the minimum unit of programming and reading, although more than one page may be programmed or read in parallel in different sub-arrays or planes of memory cells. Each page typically stores one or more sectors of data, the size of the sector being defined by the host system. An example sector includes 512 bytes of user data, following a standard established with magnetic disk drives, plus some number of bytes of overhead information about the user data and/or the block in which they are stored. Such memories are typically configured with 16, 32 or more pages within each block, and each page stores one or more host sectors of data.
In order to increase the degree of parallelism during programming user data into the memory array and read user data from it, the array is typically divided into sub-arrays, commonly referred to as planes, which contain their own data registers and other circuits to allow parallel operation such that sectors of data may be programmed to or read from each of several or all the planes simultaneously. An array on a single integrated circuit may be physically divided into planes, or each plane may be formed from a separate one or more integrated circuit chips. Examples of such a memory implementation are described in U.S. Pat. Nos. 5,798,968 and 5,890,192.
To further efficiently manage the memory, blocks may be linked together to form virtual blocks or metablocks. That is, each metablock is defined to include one block from each of several or all of the planes. Use of the metablock is described in U.S. patent application publication No. 2002/0099904. The metablock is identified by a host logical block address as a destination for programming and reading data. Similarly, all blocks of a metablock are typically erased together.
The controller in a memory system operated with such large blocks and/or metablocks performs a number of functions imposed upon it by the host and in order to maintain efficient operation. Repetitive data consolidation (“garbage collection”) is performed in order to efficiently utilize the storage capacity of the memory. The controller typically suspends its primary function of transferring data into and out of the memory when performing garbage collection, thus potentially adversely affecting system performance. Some limited copying of data on the memory array chips themselves is disclosed in U.S. Pat. No. 6,266,273.
A typical flash memory system includes one or more integrated circuit chips that each contains an array of memory cells and associated peripheral circuitry, and another integrated circuit chip containing the controller. For some applications, a controller and a memory array are included on a single chip. In either case, data, addresses, commands and status information are communicated between the controller and one or more flash memory cell arrays, sub-arrays, planes or integrated circuit chips over a common bi-directional system bus to which all of the memory system components are operably connected.